1. Field
This disclosure relates to generating and receiving traffic for testing a network or network device.
2. Description of the Related Art
In many types of communications networks, each message to be sent is divided into portions of fixed or variable length. Each portion may be referred to as a packet, a frame, a cell, a datagram, a data unit, or other unit of information, all of which are referred to herein as packets.
Each packet contains a portion of an original message, commonly called the payload of the packet. The payload of a packet may contain data, or may contain voice or video information. The payload of a packet may also contain network management and control information. In addition, each packet contains identification and routing information, commonly called a packet header. The packets are sent individually over the network through multiple switches or nodes. The packets are reassembled into the message at a final destination using the information contained in the packet headers, before the message is delivered to a target device or end user. At the receiving end, the reassembled message is passed to the end user in a format compatible with the user's equipment.
Communications networks that transmit messages as packets are called packet switched networks. Packet switched networks commonly contain a mesh of transmission paths which intersect at hubs or nodes. At least some of the nodes may include a switching device or router that receives packets arriving at the node and retransmits the packets along appropriate outgoing paths. Packet switched networks are governed by a layered structure of industry-standard protocols.
In order to test a packet switched network or a device included in a packet switched communications network, test traffic comprising a large number of packets may be generated, transmitted into the network at one or more ports, and received at different ports. Each packet in the test traffic may be a unicast packet intended for reception at a specific destination port or a multicast packet, which may be intended for reception at two or more destination ports. In this context, the term “port” refers to a communications connection between the network and the equipment used to test the network. The term “port unit” refers to a module within the network test equipment that connects to the network at a port. The received test traffic may be analyzed to measure the performance of the network. Each port unit connected to the network may be both a source of test traffic and a destination for test traffic. Each port unit may emulate a plurality of logical source and/or destination addresses. The number of port units and the communications paths that connect the port units to the network are typically fixed for the duration of a test session. The internal structure of the network may change during a test session, for example due to failure of a communications path or hardware device.
A series of packets originating from a single port unit and having a specific type of packet and a specific rate will be referred to herein as a “stream.” A source port unit may support multiple outgoing streams simultaneously and concurrently, for example to accommodate multiple packet types, rates, or destinations. “Simultaneously” means “at exactly the same time.” “Concurrently” means “within the same time.”
A plurality of concurrent streams may be combined to form the test traffic output from a source port. The streams within the test traffic may be transmitted sequentially or concurrently through interleaving. The interleaving may be balanced, unbalanced, and distributed among the represented streams. To test a modern “triple play” network and network equipment, the test traffic may contain simulated data, audio, and video streams.
The test traffic may be divided into a plurality of “traffic items”, where each traffic item is effectively a separate test from each other traffic item. Test traffic for some or all of a plurality of traffic items may be generated and transmitted concurrently. Each traffic items may include a plurality of streams, and each stream may typically be a portion of a single traffic item.
For the purpose of collecting test data, the test traffic for each traffic item may be organized into packet groups, where a “packet group” is any plurality of packets for which network traffic statistics are accumulated. The packets in a given packet group may be distinguished by a packet group identifier (PGID) contained in each packet. The PGID may be, for example, a dedicated identifier field or combination of two or more fields within each packet.
For the purpose of reporting network traffic data, the test traffic for each traffic item may be organized into flows, where a “flow” is any plurality of packets for which network traffic statistics are reported. Each flow may consist of a single packet group or a small plurality of packet groups. Each packet group may typically belong to a single flow.
Within this description, the term “engine” means a collection of hardware, which may be augmented by firmware and/or software, which performs the described functions. An engine may typically be designed using a hardware description language (HDL) that defines the engine primarily in functional terms. The HDL design may be verified using an HDL simulation tool. The verified HDL design may then be converted into a gate netlist or other physical description of the engine in a process commonly termed “synthesis”. The synthesis may be performed automatically using a synthesis tool. The gate netlist or other physical description may be further converted into programming code for implementing the engine in a programmable device such as a field programmable gate array (FPGA), a programmable logic device (PLD), or a programmable logic arrays (PLA). The gate netlist or other physical description may be converted into process instructions and masks for fabricating the engine within an application specific integrated circuit (ASIC).
Within this description, a hardware “unit” also means a collection of hardware, which may be augmented by firmware and/or software, which may be on a larger scale than an “engine”. For example, a unit may contain multiple engines, some of which may perform similar functions in parallel. The terms “engine” and “unit” do not imply any physical separation or demarcation. All or portions of one or more units and/or engines may be collocated on a common card, such as a network card 114, or within a common FPGA, ASIC, or other circuit device.
In this description, the term “logic” is intended to encompass combinatorial logic circuits, sequential elements such as latches and registers, adaptive logic circuits and/or processors controlled by firmware, and other digital circuits that perform a specified function. An engine may include a plurality of logic elements.
Throughout this description, elements appearing in block diagrams are assigned three-digit reference designators, where the most significant digit is the figure number and the two least significant digits are specific to the element. An element that is not described in conjunction with a block diagram may be presumed to have the same characteristics and function as a previously-described element having a reference designator with the same least significant digits.
In block diagrams, arrow-terminated lines may indicate data paths rather than signals. Each data path may be multiple bits in width. For example, each data path may consist of 4, 8, 16, 32, 64, or more parallel connections.